The present invention relates to a peripheral circuit in a memory system.
In a dynamic memory system, the output of a peripheral circuit such as an address buffer circuit or a driver circuit is reduced to zero volt (for an N-channel system) by an inverted external clock signal, i.e., by a so-called precharge signal prior to the initiation of the readout or write operations, i.e. in a stand-by period. When the external clock changes from zero volt to a high voltage (power supply voltage V.sub.D), the memory system is rendered operative but the peripheral circuit does not operate even after the external clock has changed to the high voltage until the precharge signal becomes zero volt.
The precharge signal necessarily includes a delay time because it is generated by the external clock in an IC chip.
The delay time of the prior art precharge signal generating circuit amounts to 20-30 nanoseconds because only one precharge signal generating circuit has been used to precharge all of the peripheral circuits in the IC chip.
It is an address buffer circuit which is operated first on the peripheral circuit that poses a critical problem due to the delay time because such delay time is directly added to the delay time of the address buffer circuit resulting in the increase in an access time and blocking the realization of a high speed system.